Power supply circuits usually have a configuration containing a high side power MOS transistor and/or a low side power MOS transistor. The high side power MOS transistor may be coupled between a supply node for receiving a supply voltage and an output node for providing the supply voltage, and the low side power MOS transistor may be coupled between the output node and a reference node for receiving a reference voltage which is lower than the supply voltage. These two power MOS transistors may be turned on or off to selectively supply power to external loads.
Inductive external loads require a stable output to avoid oscillation. Therefore, current limiting circuits are widely used in power supply circuits to limit the output current of power supply circuits.
FIG. 1 shows a conventional current limiting circuit. As shown in FIG. 1, a high side power PMOS transistor MP1 is coupled between a supply voltage VINHSD and an output node HSD to provide the supply voltage to external loads. A current source Ib1 and a resistor R2 are coupled in series between the supply voltage and ground. The current provided by current source Ib1 is determined by a resistor (not shown; referred to as R1) and a band gap reference voltage VBG. The voltage at a node G1 at which R2 and Ib1 are coupled with each other is applied to a gate terminal of Mp1 via a resistor R3.
Moreover, a PNP bipolar transistor Q4 and a diode D1 are coupled in series (between VINHSD and node G1), and together in parallel with the second resistor R2, with an emitter terminal of Q4 coupled to VINHSD.
A current mirror having a first branch and a second branch is coupled between the supply voltage VINHSD and ground. The first branch has a resistor R4, a PNP bipolar transistor Q1 and a current source Ib3 coupled in series, wherein R4 is coupled between VINHSD and an emitter terminal of Q1, and Ib3 is coupled between a collector terminal of Q1 and ground. The second branch has a PNP bipolar transistor Q2 and a current source Ib2 coupled in series, wherein an emitter terminal of Q2 is coupled with VINHSD, and Ib2 is coupled with ground. Base terminals of Q1 and Q2 are coupled together and further coupled to a collector terminal of Q2.
R4 is also coupled between the supply voltage VINHSD and a source terminal of PMOS high side power transistor MP1. The base terminal of Q4 is coupled to a collector terminal of Q1. Specifically, the current provided by Ib2 is identical to current provided by Ib3. Current gain ratio of transistor Q1 and Q2 is N:1, wherein N is an integer no less than 1.
In operation, resistor R4 may function as a current sensing resistor for sensing the output current flowing through the high side power PMOS transistor MP1. Changes of output current may cause changes of voltage drop across resistor R4, and may consequently be rippled to influence the voltage at node G1 through the current mirror and bipolar transistor Q4. Therefore, the gate-source voltage of the high side power PMOS transistor MP1 may be adjusted which may limit the output current of MP1 accordingly.
Thus, the output current supplied by the high side power PMOS transistor MP1 can be limited to
      I    load    =                    V        T                    R        4              ⁢    ln    ⁢                  ⁢          N      .      The current limiting circuit in FIG. 1 is a high gain loop which is configured to adjust the output current of MP1 when a sudden peak appears. However, such a configuration may suffer from stableness problem since the limiting circuit may drag the output current to negative and cause oscillation. Therefore, a branch including a resistor R5 and a capacitor C1 coupled in series is needed for compensation, wherein R5 is coupled with VINHSD and C1 is coupled to the base terminal of Q4. But compensation may lower the response speed of the current limiting process.
FIG. 2 shows another conventional current limiting circuit. Slightly different from the current limiting circuit in FIG. 1, the current limiting circuit in FIG. 2 includes a bipolar transistor Q3 in place of the compensation branch including resistor R5 and capacitor C1, wherein base terminals of Q3 and Q4 and a collector terminal of Q3 are coupled to the collector terminal of Q1. The current gain ratio of Q3 and Q4 is M:1, wherein M is an integer no less than 1. The current limiting circuit in FIG. 2 is a low gain loop which has a better stability than the current limiting circuit in FIG. 1 but suffers from a relatively slow response.
Both of the above two conventional current limiting circuits employ R4 as a sensing resistor to sense changes of the output current of the power transistor. The voltage drop across resistor R4 should be tens of mV to ensure the reliability of the current limiting circuits. However, in order to pass a short-to-plus-unpowered (SPU) test (generally greater than 100 A), the resistance of resistor R4 may only be around 2 mΩ. Therefore, under such a condition, resistor R4 cannot generate a suitable voltage drop to avoid reliability issue when the output current is limited to around 1 A.
Also, using R4 to sense the output current change may increase the on-resistance when providing the supply voltage to the external loads.
FIG. 3 shows another conventional current limiting circuit. As shown in FIG. 3, the current limiting circuit has a high side power PMOS transistor Mp1 and a PMOS transistor M2 forming a current mirror which has a current gain determined by width-to-length ratios of the two transistors, for example the width-to-length ratio of Mp1 may be K times that of M2. The gate and drain terminals of M2 are coupled together with a current source Ib. Therefore, the voltage at a gate terminal of the power PMOS transistor Mp1 is determined by the current source Ib as well as the width-to-length ratios of Mp1 and M2. In this way, the output current flowing through the high side power MOS transistor Mp1 can be limited to Iload=IbK.
Even though the current limiting circuit in FIG. 3 may accurately limit the output current of the power transistor, such a current limiting circuit has a high on-resistance when providing the supply voltage to external loads which is not preferred due to high power consumption.